.TH "mcuconf.h" 3 "Wed Sep 16 2015" "Doxygen" \" -*- nroff -*-
.ad l
.nh
.SH NAME
mcuconf.h \- 
.SH SYNOPSIS
.br
.PP
.SS "Macros"

.in +1c
.ti -1c
.RI "#define \fBSTM32F4xx_MCUCONF\fP"
.br
.ti -1c
.RI "#define \fBSTM32_NO_INIT\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_HSI_ENABLED\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_LSI_ENABLED\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_HSE_ENABLED\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_LSE_ENABLED\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_CLOCK48_REQUIRED\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_SW\fP   STM32_SW_PLL"
.br
.ti -1c
.RI "#define \fBSTM32_PLLSRC\fP   STM32_PLLSRC_HSE"
.br
.ti -1c
.RI "#define \fBSTM32_PLLM_VALUE\fP   8"
.br
.ti -1c
.RI "#define \fBSTM32_PLLN_VALUE\fP   336"
.br
.ti -1c
.RI "#define \fBSTM32_PLLP_VALUE\fP   2"
.br
.ti -1c
.RI "#define \fBSTM32_PLLQ_VALUE\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_HPRE\fP   STM32_HPRE_DIV1"
.br
.ti -1c
.RI "#define \fBSTM32_PPRE1\fP   STM32_PPRE1_DIV4"
.br
.ti -1c
.RI "#define \fBSTM32_PPRE2\fP   STM32_PPRE2_DIV2"
.br
.ti -1c
.RI "#define \fBSTM32_RTCSEL\fP   STM32_RTCSEL_LSI"
.br
.ti -1c
.RI "#define \fBSTM32_RTCPRE_VALUE\fP   8"
.br
.ti -1c
.RI "#define \fBSTM32_MCO1SEL\fP   STM32_MCO1SEL_HSI"
.br
.ti -1c
.RI "#define \fBSTM32_MCO1PRE\fP   STM32_MCO1PRE_DIV1"
.br
.ti -1c
.RI "#define \fBSTM32_MCO2SEL\fP   STM32_MCO2SEL_SYSCLK"
.br
.ti -1c
.RI "#define \fBSTM32_MCO2PRE\fP   STM32_MCO2PRE_DIV5"
.br
.ti -1c
.RI "#define \fBSTM32_I2SSRC\fP   STM32_I2SSRC_CKIN"
.br
.ti -1c
.RI "#define \fBSTM32_PLLI2SN_VALUE\fP   192"
.br
.ti -1c
.RI "#define \fBSTM32_PLLI2SR_VALUE\fP   5"
.br
.ti -1c
.RI "#define \fBSTM32_PVD_ENABLE\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_PLS\fP   STM32_PLS_LEV0"
.br
.ti -1c
.RI "#define \fBSTM32_BKPRAM_ENABLE\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADCPRE\fP   ADC_CCR_ADCPRE_DIV4"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_USE_ADC1\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_USE_ADC2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_USE_ADC3\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC1_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 4)"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC2_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 2)"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC3_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 1)"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC1_DMA_PRIORITY\fP   2"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC2_DMA_PRIORITY\fP   2"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC3_DMA_PRIORITY\fP   2"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC1_DMA_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC2_DMA_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_ADC_ADC3_DMA_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_CAN_USE_CAN1\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_CAN_USE_CAN2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_CAN_CAN1_IRQ_PRIORITY\fP   11"
.br
.ti -1c
.RI "#define \fBSTM32_CAN_CAN2_IRQ_PRIORITY\fP   11"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI0_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI1_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI2_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI3_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI4_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI5_9_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI10_15_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI16_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI17_IRQ_PRIORITY\fP   15"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI18_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI19_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI20_IRQ_PRIORITY\fP   6"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI21_IRQ_PRIORITY\fP   15"
.br
.ti -1c
.RI "#define \fBSTM32_EXT_EXTI22_IRQ_PRIORITY\fP   15"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_USE_TIM1\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_USE_TIM2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_USE_TIM3\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_USE_TIM4\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_USE_TIM5\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_USE_TIM8\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_TIM1_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_TIM2_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_TIM3_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_TIM4_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_TIM5_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_GPT_TIM8_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_USE_I2C1\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_USE_I2C2\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_USE_I2C3\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C1_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 0)"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C1_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 6)"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C2_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 2)"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C2_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 7)"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C3_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 2)"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C3_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 4)"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C1_IRQ_PRIORITY\fP   5"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C2_IRQ_PRIORITY\fP   5"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C3_IRQ_PRIORITY\fP   5"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C1_DMA_PRIORITY\fP   3"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C2_DMA_PRIORITY\fP   3"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C3_DMA_PRIORITY\fP   3"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C1_DMA_ERROR_HOOK\fP()         chSysHalt()"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C2_DMA_ERROR_HOOK\fP()         chSysHalt()"
.br
.ti -1c
.RI "#define \fBSTM32_I2C_I2C3_DMA_ERROR_HOOK\fP()         chSysHalt()"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_USE_TIM1\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_USE_TIM2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_USE_TIM3\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_USE_TIM4\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_USE_TIM5\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_USE_TIM8\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_TIM1_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_TIM2_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_TIM3_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_TIM4_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_TIM5_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_ICU_TIM8_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_USE_ADVANCED\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_USE_TIM1\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_USE_TIM2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_USE_TIM3\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_USE_TIM4\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_USE_TIM5\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_USE_TIM8\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_TIM1_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_TIM2_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_TIM3_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_TIM4_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_TIM5_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_PWM_TIM8_IRQ_PRIORITY\fP   7"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USE_USART1\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USE_USART2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USE_USART3\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USE_UART4\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USE_UART5\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USE_USART6\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USART1_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USART2_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USART3_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_UART4_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_UART5_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_SERIAL_USART6_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_USE_SPI1\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_USE_SPI2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_USE_SPI3\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI1_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 0)"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI1_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 3)"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI2_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 3)"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI2_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 4)"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI3_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 0)"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI3_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 7)"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI1_DMA_PRIORITY\fP   1"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI2_DMA_PRIORITY\fP   1"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI3_DMA_PRIORITY\fP   1"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI1_IRQ_PRIORITY\fP   10"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI2_IRQ_PRIORITY\fP   10"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_SPI3_IRQ_PRIORITY\fP   10"
.br
.ti -1c
.RI "#define \fBSTM32_SPI_DMA_ERROR_HOOK\fP(spip)           chSysHalt()"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USE_USART1\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USE_USART2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USE_USART3\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USE_USART6\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART1_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 5)"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART1_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 7)"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART2_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 5)"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART2_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 6)"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART3_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 1)"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART3_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(1, 3)"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART6_RX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 2)"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART6_TX_DMA_STREAM\fP   STM32_DMA_STREAM_ID(2, 7)"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART1_IRQ_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART2_IRQ_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART3_IRQ_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART6_IRQ_PRIORITY\fP   12"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART1_DMA_PRIORITY\fP   0"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART2_DMA_PRIORITY\fP   0"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART3_DMA_PRIORITY\fP   0"
.br
.ti -1c
.RI "#define \fBSTM32_UART_USART6_DMA_PRIORITY\fP   0"
.br
.ti -1c
.RI "#define \fBSTM32_UART_DMA_ERROR_HOOK\fP(uartp)       chSysHalt()"
.br
.ti -1c
.RI "#define \fBSTM32_USB_USE_OTG1\fP   TRUE"
.br
.ti -1c
.RI "#define \fBSTM32_USB_USE_OTG2\fP   FALSE"
.br
.ti -1c
.RI "#define \fBSTM32_USB_OTG1_IRQ_PRIORITY\fP   14"
.br
.ti -1c
.RI "#define \fBSTM32_USB_OTG2_IRQ_PRIORITY\fP   14"
.br
.ti -1c
.RI "#define \fBSTM32_USB_OTG1_RX_FIFO_SIZE\fP   512"
.br
.ti -1c
.RI "#define \fBSTM32_USB_OTG2_RX_FIFO_SIZE\fP   1024"
.br
.ti -1c
.RI "#define \fBSTM32_USB_OTG_THREAD_PRIO\fP   LOWPRIO"
.br
.ti -1c
.RI "#define \fBSTM32_USB_OTG_THREAD_STACK_SIZE\fP   128"
.br
.ti -1c
.RI "#define \fBSTM32_USB_OTGFIFO_FILL_BASEPRI\fP   0"
.br
.in -1c
.SH "Macro Definition Documentation"
.PP 
.SS "#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY   6"

.SS "#define STM32_ADC_ADC1_DMA_PRIORITY   2"

.SS "#define STM32_ADC_ADC1_DMA_STREAM   STM32_DMA_STREAM_ID(2, 4)"

.SS "#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY   6"

.SS "#define STM32_ADC_ADC2_DMA_PRIORITY   2"

.SS "#define STM32_ADC_ADC2_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)"

.SS "#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY   6"

.SS "#define STM32_ADC_ADC3_DMA_PRIORITY   2"

.SS "#define STM32_ADC_ADC3_DMA_STREAM   STM32_DMA_STREAM_ID(2, 1)"

.SS "#define STM32_ADC_ADCPRE   ADC_CCR_ADCPRE_DIV4"

.SS "#define STM32_ADC_IRQ_PRIORITY   6"

.SS "#define STM32_ADC_USE_ADC1   FALSE"

.SS "#define STM32_ADC_USE_ADC2   FALSE"

.SS "#define STM32_ADC_USE_ADC3   FALSE"

.SS "#define STM32_BKPRAM_ENABLE   FALSE"

.SS "#define STM32_CAN_CAN1_IRQ_PRIORITY   11"

.SS "#define STM32_CAN_CAN2_IRQ_PRIORITY   11"

.SS "#define STM32_CAN_USE_CAN1   TRUE"

.SS "#define STM32_CAN_USE_CAN2   FALSE"

.SS "#define STM32_CLOCK48_REQUIRED   TRUE"

.SS "#define STM32_EXT_EXTI0_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI10_15_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI16_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI17_IRQ_PRIORITY   15"

.SS "#define STM32_EXT_EXTI18_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI19_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI1_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI20_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI21_IRQ_PRIORITY   15"

.SS "#define STM32_EXT_EXTI22_IRQ_PRIORITY   15"

.SS "#define STM32_EXT_EXTI2_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI3_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI4_IRQ_PRIORITY   6"

.SS "#define STM32_EXT_EXTI5_9_IRQ_PRIORITY   6"

.SS "#define STM32_GPT_TIM1_IRQ_PRIORITY   7"

.SS "#define STM32_GPT_TIM2_IRQ_PRIORITY   7"

.SS "#define STM32_GPT_TIM3_IRQ_PRIORITY   7"

.SS "#define STM32_GPT_TIM4_IRQ_PRIORITY   7"

.SS "#define STM32_GPT_TIM5_IRQ_PRIORITY   7"

.SS "#define STM32_GPT_TIM8_IRQ_PRIORITY   7"

.SS "#define STM32_GPT_USE_TIM1   FALSE"

.SS "#define STM32_GPT_USE_TIM2   FALSE"

.SS "#define STM32_GPT_USE_TIM3   FALSE"

.SS "#define STM32_GPT_USE_TIM4   FALSE"

.SS "#define STM32_GPT_USE_TIM5   FALSE"

.SS "#define STM32_GPT_USE_TIM8   FALSE"

.SS "#define STM32_HPRE   STM32_HPRE_DIV1"

.SS "#define STM32_HSE_ENABLED   TRUE"

.SS "#define STM32_HSI_ENABLED   TRUE"

.SS "#define STM32_I2C_I2C1_DMA_ERROR_HOOK()   chSysHalt()"

.SS "#define STM32_I2C_I2C1_DMA_PRIORITY   3"

.SS "#define STM32_I2C_I2C1_IRQ_PRIORITY   5"

.SS "#define STM32_I2C_I2C1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)"

.SS "#define STM32_I2C_I2C1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)"

.SS "#define STM32_I2C_I2C2_DMA_ERROR_HOOK()   chSysHalt()"

.SS "#define STM32_I2C_I2C2_DMA_PRIORITY   3"

.SS "#define STM32_I2C_I2C2_IRQ_PRIORITY   5"

.SS "#define STM32_I2C_I2C2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)"

.SS "#define STM32_I2C_I2C2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)"

.SS "#define STM32_I2C_I2C3_DMA_ERROR_HOOK()   chSysHalt()"

.SS "#define STM32_I2C_I2C3_DMA_PRIORITY   3"

.SS "#define STM32_I2C_I2C3_IRQ_PRIORITY   5"

.SS "#define STM32_I2C_I2C3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)"

.SS "#define STM32_I2C_I2C3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)"

.SS "#define STM32_I2C_USE_I2C1   FALSE"

.SS "#define STM32_I2C_USE_I2C2   TRUE"

.SS "#define STM32_I2C_USE_I2C3   FALSE"

.SS "#define STM32_I2SSRC   STM32_I2SSRC_CKIN"

.SS "#define STM32_ICU_TIM1_IRQ_PRIORITY   7"

.SS "#define STM32_ICU_TIM2_IRQ_PRIORITY   7"

.SS "#define STM32_ICU_TIM3_IRQ_PRIORITY   7"

.SS "#define STM32_ICU_TIM4_IRQ_PRIORITY   7"

.SS "#define STM32_ICU_TIM5_IRQ_PRIORITY   7"

.SS "#define STM32_ICU_TIM8_IRQ_PRIORITY   7"

.SS "#define STM32_ICU_USE_TIM1   FALSE"

.SS "#define STM32_ICU_USE_TIM2   FALSE"

.SS "#define STM32_ICU_USE_TIM3   TRUE"

.SS "#define STM32_ICU_USE_TIM4   FALSE"

.SS "#define STM32_ICU_USE_TIM5   FALSE"

.SS "#define STM32_ICU_USE_TIM8   FALSE"

.SS "#define STM32_LSE_ENABLED   FALSE"

.SS "#define STM32_LSI_ENABLED   TRUE"

.SS "#define STM32_MCO1PRE   STM32_MCO1PRE_DIV1"

.SS "#define STM32_MCO1SEL   STM32_MCO1SEL_HSI"

.SS "#define STM32_MCO2PRE   STM32_MCO2PRE_DIV5"

.SS "#define STM32_MCO2SEL   STM32_MCO2SEL_SYSCLK"

.SS "#define STM32_NO_INIT   FALSE"

.SS "#define STM32_PLLI2SN_VALUE   192"

.SS "#define STM32_PLLI2SR_VALUE   5"

.SS "#define STM32_PLLM_VALUE   8"

.SS "#define STM32_PLLN_VALUE   336"

.SS "#define STM32_PLLP_VALUE   2"

.SS "#define STM32_PLLQ_VALUE   7"

.SS "#define STM32_PLLSRC   STM32_PLLSRC_HSE"

.SS "#define STM32_PLS   STM32_PLS_LEV0"

.SS "#define STM32_PPRE1   STM32_PPRE1_DIV4"

.SS "#define STM32_PPRE2   STM32_PPRE2_DIV2"

.SS "#define STM32_PVD_ENABLE   FALSE"

.SS "#define STM32_PWM_TIM1_IRQ_PRIORITY   7"

.SS "#define STM32_PWM_TIM2_IRQ_PRIORITY   7"

.SS "#define STM32_PWM_TIM3_IRQ_PRIORITY   7"

.SS "#define STM32_PWM_TIM4_IRQ_PRIORITY   7"

.SS "#define STM32_PWM_TIM5_IRQ_PRIORITY   7"

.SS "#define STM32_PWM_TIM8_IRQ_PRIORITY   7"

.SS "#define STM32_PWM_USE_ADVANCED   FALSE"

.SS "#define STM32_PWM_USE_TIM1   FALSE"

.SS "#define STM32_PWM_USE_TIM2   FALSE"

.SS "#define STM32_PWM_USE_TIM3   FALSE"

.SS "#define STM32_PWM_USE_TIM4   FALSE"

.SS "#define STM32_PWM_USE_TIM5   FALSE"

.SS "#define STM32_PWM_USE_TIM8   FALSE"

.SS "#define STM32_RTCPRE_VALUE   8"

.SS "#define STM32_RTCSEL   STM32_RTCSEL_LSI"

.SS "#define STM32_SERIAL_UART4_PRIORITY   12"

.SS "#define STM32_SERIAL_UART5_PRIORITY   12"

.SS "#define STM32_SERIAL_USART1_PRIORITY   12"

.SS "#define STM32_SERIAL_USART2_PRIORITY   12"

.SS "#define STM32_SERIAL_USART3_PRIORITY   12"

.SS "#define STM32_SERIAL_USART6_PRIORITY   12"

.SS "#define STM32_SERIAL_USE_UART4   FALSE"

.SS "#define STM32_SERIAL_USE_UART5   FALSE"

.SS "#define STM32_SERIAL_USE_USART1   FALSE"

.SS "#define STM32_SERIAL_USE_USART2   FALSE"

.SS "#define STM32_SERIAL_USE_USART3   FALSE"

.SS "#define STM32_SERIAL_USE_USART6   FALSE"

.SS "#define STM32_SPI_DMA_ERROR_HOOK(spip)   chSysHalt()"

.SS "#define STM32_SPI_SPI1_DMA_PRIORITY   1"

.SS "#define STM32_SPI_SPI1_IRQ_PRIORITY   10"

.SS "#define STM32_SPI_SPI1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 0)"

.SS "#define STM32_SPI_SPI1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)"

.SS "#define STM32_SPI_SPI2_DMA_PRIORITY   1"

.SS "#define STM32_SPI_SPI2_IRQ_PRIORITY   10"

.SS "#define STM32_SPI_SPI2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)"

.SS "#define STM32_SPI_SPI2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)"

.SS "#define STM32_SPI_SPI3_DMA_PRIORITY   1"

.SS "#define STM32_SPI_SPI3_IRQ_PRIORITY   10"

.SS "#define STM32_SPI_SPI3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)"

.SS "#define STM32_SPI_SPI3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)"

.SS "#define STM32_SPI_USE_SPI1   FALSE"

.SS "#define STM32_SPI_USE_SPI2   FALSE"

.SS "#define STM32_SPI_USE_SPI3   FALSE"

.SS "#define STM32_SW   STM32_SW_PLL"

.SS "#define STM32_UART_DMA_ERROR_HOOK(uartp)   chSysHalt()"

.SS "#define STM32_UART_USART1_DMA_PRIORITY   0"

.SS "#define STM32_UART_USART1_IRQ_PRIORITY   12"

.SS "#define STM32_UART_USART1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 5)"

.SS "#define STM32_UART_USART1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)"

.SS "#define STM32_UART_USART2_DMA_PRIORITY   0"

.SS "#define STM32_UART_USART2_IRQ_PRIORITY   12"

.SS "#define STM32_UART_USART2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 5)"

.SS "#define STM32_UART_USART2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)"

.SS "#define STM32_UART_USART3_DMA_PRIORITY   0"

.SS "#define STM32_UART_USART3_IRQ_PRIORITY   12"

.SS "#define STM32_UART_USART3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 1)"

.SS "#define STM32_UART_USART3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)"

.SS "#define STM32_UART_USART6_DMA_PRIORITY   0"

.SS "#define STM32_UART_USART6_IRQ_PRIORITY   12"

.SS "#define STM32_UART_USART6_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)"

.SS "#define STM32_UART_USART6_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)"

.SS "#define STM32_UART_USE_USART1   FALSE"

.SS "#define STM32_UART_USE_USART2   FALSE"

.SS "#define STM32_UART_USE_USART3   TRUE"

.SS "#define STM32_UART_USE_USART6   TRUE"

.SS "#define STM32_USB_OTG1_IRQ_PRIORITY   14"

.SS "#define STM32_USB_OTG1_RX_FIFO_SIZE   512"

.SS "#define STM32_USB_OTG2_IRQ_PRIORITY   14"

.SS "#define STM32_USB_OTG2_RX_FIFO_SIZE   1024"

.SS "#define STM32_USB_OTG_THREAD_PRIO   LOWPRIO"

.SS "#define STM32_USB_OTG_THREAD_STACK_SIZE   128"

.SS "#define STM32_USB_OTGFIFO_FILL_BASEPRI   0"

.SS "#define STM32_USB_USE_OTG1   TRUE"

.SS "#define STM32_USB_USE_OTG2   FALSE"

.SS "#define STM32F4xx_MCUCONF"

.SH "Author"
.PP 
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